1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more particularly to a semiconductor memory device which is improved so that effective capacitance of a capacitor can be increased without enlarging the cell area of a memory cell.
The present invention also relates to a method of manufacturing such a semiconductor memory device. Moreover, the present invention relates to a method of manufacturing a semiconductor memory device which is improved so that damage to a cylindrical capacitor can be prevented upon megasonic cleaning or the like.
2. Description of the Background Art
FIGS. 28 to 30 are cross sectional views of a semiconductor memory device in the order of the steps performed in a manufacturing process of the semiconductor memory device according to a first conventional example disclosed in Japanese Patent Laying-Open No. 6-196649.
Referring to FIG. 28, an interlayer insulating film 2 is formed on a semiconductor substrate 1. A silicon oxide film 3 formed by CVD (Chemical Vapor Deposition) to which no impurity is added is formed on interlayer insulating film 2. A contact hole 100 is formed in interlayer insulating film 2 and silicon oxide film 3, penetrating these films to expose a portion of the surface of semiconductor substrate 1. A lower electrode 4 of a capacitor made of phosphorous doped polycrystalline silicon film is formed to be in connection with the surface of semiconductor substrate 1 through contact hole 100. Lower electrode 4 consists of an axis portion 4a extending upwards from the surface of semiconductor substrate 1, a bottom surface portion 4b extending horizontally over silicon oxide film 3, and a perpendicular portion 4c provided along the periphery of bottom surface portion 4b and extending upwards. A cylinder is formed by horizontal portion 4b and perpendicular portion 4c. A BPSG (Boro-Phospho Silicate Glass) film 5 to which impurities such as boron and phosphorus are added is buried in the cylinder of lower electrode 4.
Referring to FIGS. 28 and 29, BPSG film 5 is removed by a gas phase hydrogen fluoride treatment so as to expose the inner surface of the cylinder of lower electrode 4.
Referring to FIG. 30, a dielectric film (ON film) 6 formed by silicon oxide film and silicon nitride film is deposited entirely on the surface of semiconductor substrate 1, and an upper electrode 7 of the capacitor formed by phosphorous doped polycrystalline silicon film is stacked on this ON film 6. Thus, the capacitor is completed.
Referring to FIG. 28, gas phase hydrogen fluoride treatment is performed when removing BPSG film 5 in the conventional manufacturing method of the semiconductor memory device. When removing BPSG film 5, hydrogen fluoride exhibits an extremely high selectivity as compared to silicon oxide film 3 which does not contain impurities. As a result, the amount of the etched BPSG film would be extremely large as compared to the amount of etched silicon oxide film 3, such that the inner surface of the cylinder of lower electrode 4 can be exposed without etching silicon oxide film 3.
FIGS. 31 to 33 are cross sectional views of a semiconductor device showing the respective steps performed in a method of manufacturing a semiconductor memory device according to a second conventional example, disclosed in Japanese Patent Laying-Open No. 2-219264.
Referring to FIG. 31, a gate oxide film 8 is formed on a semiconductor substrate 1, and on this gate oxide film 8 is formed a gate electrode 9. Gate electrode 9 is covered with an insulating film 10. A polycrystalline silicon pad 11 is formed on semiconductor substrate 1 so as to be in contact with an active region of semiconductor substrate 1. Thereafter, an interlayer insulating film 2, a silicon nitride film 12 and a BPSG film 5 are formed on semiconductor substrate 1. A contact hole is formed in BPSG film 5, silicon nitride film 12 and interlayer insulating film 2, penetrating these films to expose the surface of polycrystalline silicon pad 11. A lower electrode 4 connected to polycrystalline silicon pad 11 through the contact hole is formed. Lower electrode 4 consists of a cylindrical portion and a horizontal portion attached to the upper end of this cylindrical portion to extend horizontally.
Referring to FIGS. 31 and 32, BPSG film 5 is subjected to etching under a condition in which the etching ratio of BPSG film 5 is higher with respect to lower electrode 4. By this etching, BPSG film 5 is removed.
Referring to FIG. 33, lower electrode 4 is covered with a dielectric film 6. Thereafter, an upper electrode (opposite electrode) 7 is stacked on semiconductor substrate 1 so as to cover lower electrode 4 with dielectric film 6 therebetween. Thus, the capacitor is completed.
According to this method, the upper and lower surfaces of the horizontal portion of lower electrode 4 as well as the outer and inner sides of the cylindrical portion of lower electrode 4 also contribute to the capacitance of the capacitor, so that the effective capacitance of the capacitor can be increased.
The method of manufacturing a conventional semiconductor memory device is performed as described above, providing an approach to increase the capacitance of the capacitor. Considering the fact that the cell area tends to be made smaller as DRAMs are being integrated to a higher degree, there is a need to further increase the capacitance of the capacitor without enlarging the cell area of the memory cell.
However, referring to FIG. 32, since the horizontal portion of lower electrode 4 is separated from interlayer insulating film 2 in the second conventional technique, the strength of a connecting portion 4d for providing connection between the horizontal portion of lower electrode 4 and cylindrical portion of the capacitor buried in the contact hole would be degraded. Since the connecting portion is entirely formed of silicon filled with crystal grains, megasonic cleaning or the like would apply a force owing to vibration between the crystal grains such that lower electrode 4 would break at connecting portion 4d.